1. Field of the Invention
The present invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device such as a dynamic random access memory (DRAM) wherein it is possible to inspect contact defects between memory cells in a short period time.
2. Description of the Background Art
FIG. 18 is a block diagram showing a schematic configuration of a semiconductor memory device 502 according to a prior art.
Referring to FIG. 18, the semiconductor memory device 502 includes a memory cell array 14 having a plurality of memory cells arranged in rows and columns, an address buffer 5 which receives address signals A0 to A12 and outputs an internal row address X and an internal column address Y, and a control signal input buffer 6 which captures control signals /OE, /RAS, /CAS and /WE and outputs internal control signals INTZRAS, INTZCAS and INTZWE.
The memory cell array 14 includes memory cells MC arranged in rows and columns, a plurality of word lines WL provided to correspond to the rows of memory cells MC and bit line pairs BLP provided in correspondence with the columns of the memory cells MC. In FIG. 18, one memory cell MC, one word line WL and one bit line pair BLP are shown in an exemplary manner.
The semiconductor memory device 502 further includes a control circuit 8 which receives an internal address signal from the address buffer 5 and receives the internal control signals INTZRAS, INTZCAS and INTZWE from the control signal input buffer 6 so as to output a control signal to each block.
The control circuit 8 includes a circuit which receives the internal control signals, INTZRAS, INTZCAS and INTZWE, and outputs a signal S0, which activates the sense amplifier, and an equalizing signal BLEQ, which activates the equalizing circuit of the sense amplifier band.
The semiconductor memory device 502 further includes a row decoder 510 which decodes the row address signal X given from the address buffer 5. The row decoder 510 includes a word driver for driving the addressed row (word line) inside of the memory cell array 14 into the selected condition.
The semiconductor memory device 502 further includes a column decoder 12 which decodes the internal column address Y given from the address buffer 5 so as to generate a column selection signal and a sense amplifier band 516 wherein a plurality of sense amplifiers, which carry out detection and amplification of data of memory cells MC connected to the selected row in the memory cell array 14, are arranged.
The semiconductor memory device 502 further includes an input buffer 22 which receives writing data from the outside and generates internal writing data, a writing driver which amplifies the internal writing data from the input buffer 22 and transmits them to the selected memory cell, a preamplifier which amplifies the data read out from the selected memory cell and an output buffer 20 which further carries out buffer processing on the data from this preamplifier and outputs them to the outside.
In FIG. 18, the preamplifier and the writing driver are shown as one block, the block 18.
FIG. 19 is a circuit diagram showing the configuration of the row decoder 510 in FIG. 18.
Referring to FIG. 19, the row decoder 510 includes a pre-decoder 532, which pre-decodes the lowest two bits in the row address, a pre-decoder 536, which decodes the rest except for the lowest two bits in the row address, and a main decoder 38, which selects a word line in accordance with the outputs of the pre-decoders 532 and 536.
The pre-decoder 532 receives signals RA0 and RA1, which correspond to the lowest two bits of the row address, and signals ZRA0 and ZRA1, which are, respectively, complementary to the signals RA0 and RA1. The pre-decoder 536 receives the signals RA2 to RA12, which correspond to the row address except for the lowest two bits, and the signals ZRA2 to ZRA12, which are, respectively, complementary to the signals RA2 to RA12.
The pre-decoder 532 includes a NAND circuit 540 which receives the signals ZRA0 and ZRA1, an inverter 542 which inverts by receiving the output of the NAND circuit 540 and outputs a pre-decode signal X0, a NAND circuit 544 which receives the signals RA0 and ZRA1, and an inverter 546 which inverts by receiving the output of the NAND circuit 544 and outputs a pre-decode signal X1.
The pre-decoder 532 further includes a NAND circuit 548 which receives signals ZRA0 and RA1, an inverter 550 which inverts by receiving the output of the NAND circuit 548 and outputs a pre-decode signal X2, a NAND circuit 552 which receives signals RA0 and RA1 and an inverter 554 which inverts by receiving the output of the NAND circuit 552 and outputs a pre-decode signal X2.
The pre-decoder 536 includes the pre-decode circuits 556, 558, . . . , 560 which output, respectively, pre-decode signals RX0, RX1 . . . , RX2047.
The pre-decode circuit 556 includes a NAND circuit 562 which receives the signals ZRA2 to ZRA12, and an inverter 564 which inverts by receiving the output of the NAND circuit 562 and outputs a pre-decode signal RX0.
The pre-decode circuit 558 includes a NAND circuit 566 which receives the signal RA2 and the signals ZRA3 to ZRA12, and an inverter 568 which inverts by receiving the output of the NAND circuit 566 and outputs a pre-decode signal RX1.
The pre-decode circuit 560 includes a NAND circuit 570 which receives the signals RA2 to RA12, and an inverter 572 which inverts by receiving the output of the NAND circuit 570 and outputs a pre-decode signal RX2047.
The main decoder 38 includes decode circuits 72, 74, . . . , 76 which activate corresponding word lines in accordance with the respective pre-decode signals RX0, RX1, . . . , RX2047.
The decode circuit 72 includes a NAND circuit 78 which receives the pre-decode signals RX0 and X0, an inverter 80 which inverts by receiving the output of the NAND circuit 78, a NAND circuit 82 which receives the pre-decode signals RX0 and X1, an inverter 84 which inverts by receiving the output of the NAND circuit 82, a NAND circuit 86 which receives the pre-decode signals RX0 and X2, an inverter 88 which inverts by receiving the output of a NAND circuit 86, a NAND circuit 90 which receives the pre-decode signals RX0 and X3, and inverter 92 which inverts by receiving the output of the NAND circuit 90. The inverters 80, 84, 88 and 92 operate as word drivers for driving, respectively, the word lines WL0, WL1, WL2 and WL3.
Though the decode circuit 74 is different from the decode circuit 72 in the point that the pre-decode signal RX1 is received in place of RX0 and the word lines WL4 to WL7 are, respectively, activated in place of the word lines WL0 to WL3. Since the circuit configuration of the decode circuit 74 is similar to that of the decode circuit 72, the description is not repeated.
Though the decode circuit 76 is different from the decode circuit 72 in the point that the pre-decode signal RX2047 is received in place of RX0 and the word lines WLn-3 to WLn are, respectively, activated in place of the word lines WL0 to WL3. Since the circuit configuration of the decode circuit 76 is similar to that of the decode circuit 72, the description is not repeated.
The row decoder can, finally, select 4xc3x972048, that is to say, 8192 word lines.
FIG. 20 is a view partially showing the manner of memory cell arrangement of the memory cell array 14 as shown in FIG. 18.
Here, a part of the row decoder and a column decoder as well as sense amplifiers and bit line equalizing circuits are depicted in FIG. 20 for reference.
Referring to FIG. 20, memory cells are arranged in a so-called half pitch configuration. In the half pitch configuration, one cell is surrounded by eight adjacent cells. One of the reasons for memory cell defects is a short circuit between a storage node and a storage node (SNxe2x80x94SN) due to a short circuit between adjacent cells. As a test pattern which has a high detection performance for such defects, a surrounding pattern exists.
As shown in FIG. 20, the surrounding pattern is a test pattern wherein, with respect to a memory cell (hereinafter referred to as a noteworthy cell) which is the subject of the inspection for the occurrence of a short circuit, the eight adjacent cells (hereinafter referred to as adjacent cells) surrounding the noteworthy cell have the opposite polarity in the writing data.
FIG. 20 shows a pattern for writing xe2x80x9cHxe2x80x9d data in the noteworthy cell and xe2x80x9cLxe2x80x9d data in the eight adjacent cells. There is, of course, the case where the polarity of the writing data is reversed. In order to write the surrounding pattern in a memory cell array of the half pitch configuration, the data of the opposite polarity may be written in all of the cells of a column of every 4th word line.
The description corresponding to FIG. 20 is given as follows: in the case of the pre-decode signal X3=xe2x80x9cHxe2x80x9d, xe2x80x9cHxe2x80x9d data are written in a memory cell and in the case of pre-decode signals X0, X1, X2=xe2x80x9cH, H, Hxe2x80x9d, xe2x80x9cLxe2x80x9d data are written into a memory cell.
In the case of changing the noteworthy cell, writing may be carried out by changing the pre-decode signal which is activated from the pre-decode signal X3 to any of the pre-decode signals X0, X1 and X2.
In the case that there is a short circuit between SNxe2x80x94SN, in particular in the case that there is a short circuit between storage nodes of a plurality of adjacent memory cells, defect detection can be carried out by using a surrounding pattern. At the time of testing, first, the surrounding pattern is written into all of the bits of the memory cells according to a conventional writing function. Then, after that, no writing is carried out on the noteworthy cell and the restoring of data is repeatedly carried out on the eight adjacent cells surrounding the noteworthy cell.
Restoring is more concretely described here. For example, in the case that the word line selected by the pre-decode signal X3 is for the noteworthy cell, as shown in FIG. 20, the surrounding pattern which makes the data of the noteworthy cell xe2x80x9cHxe2x80x9d data is once written in.
After that, word lines corresponding to the pre-decode signals X0 to X2, that is to say, the word lines WL0, WL1, WL2, WL4, WL5, WL6, . . . are activated in order so that the writing of xe2x80x9cLxe2x80x9d data into a memory cell is repeated.
If there is a short circuit between SNxe2x80x94SN the potential of the noteworthy cell becomes close to the potential of the adjacent cells. The potential of the adjacent cells wherein a short circuit occurs becomes, of course, close to the potential of the noteworthy cell.
However, since restoring is carried out on the adjacent cells, the potential of the adjacent cells, which once becomes a middle potential, is again set at the potential corresponding to the xe2x80x9cLxe2x80x9d data. Then, the potential of the noteworthy cell is further lowered from the potential corresponding to the xe2x80x9cHxe2x80x9d data to the potential corresponding to the xe2x80x9cLxe2x80x9d data. Accordingly, since the potential of the noteworthy cell is soon inverted to the opposite polarity, defects can be detected when the reading is carried out.
In the case that the detection of a short circuit between SNxe2x80x94SN by means of the surrounding pattern is carried out for the memory cells of the entire surface of the memory cell array, however, it is necessary to carry out the detection by selecting the noteworthy cell in four different ways. That is to say, since there are four patterns of word lines which are to be activated for writing the opposite polarity data, the test time tends to take a long period of time in the case that these writings are carried out by means of a conventional writing function. That is to say, the operation of repeating the selection of the word lines in sequence four times is necessary in order to write a necessary surrounding pattern. Furthermore, the writing time is doubled when the inversion of the polarity of the data is taken into consideration.
An object of this invention is to provide a semiconductor memory device which can carry out the writing of a test pattern easily and in a short time over the entire surface of a memory cell array.
Briefly stated, this invention relates to a semiconductor memory device which has a normal operation mode and a test mode and includes a memory array, a plurality of bit lines, a plurality of word lines and a row decode circuit.
The memory array includes a plurality of memory cells which are arranged in rows and columns. The plurality of bit lines are arranged along the column direction and carries out the writing and the reading of data on the plurality of memory cells. The plurality of word lines are arranged along the row direction and select a particular memory cell from among the plurality of memory cells.
The plurality of word lines is divided into first to fourth word line groups. The first word line group includes word lines which correspond to the (4m+1)th, where m is a nonnegative integer, when the first word line is counted as first from among the plurality of word lines. The second word line group includes word lines which correspond to the (4m+2)th when the first word line is counted as first. The third word line group includes word lines which correspond to the (4m+3)th when the first word line is counted as first. The fourth word line group includes word lines which correspond to the (4m+4)th when the first word line is counted as first.
The row decode circuit activates the plurality of word lines, by making the first to the fourth word line groups the unit of activation, in accordance with the address signal in the test mode.
Accordingly, the main advantage of this invention is that, since a test pattern can be written into a memory cell array in a short period of time, the test time can be reduced and the production efficiency is increased.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.